DESIGN AND SIMULATION OF A 10-BIT SUCCESSIVE APPROXIMATION REGISTER ADC WITH A BOOTSTRAPPED SAMPLING SWITCH IN 180 NM CMOS

This paper describes a 10-bit successive approximation register (SAR) ADC designed in Cadence Virtuoso and simulated with Spectre on the 180 nm gpdk180 process. The converter has a bootstrapped sampling switch, a binary-weighted charge-redistribution capacitor DAC (10 fF to 5.12 pF), a StrongARM latch comparator, a 12-state SAR controller and a 10-bit output register, all driven by one 1 MHz, 5 V clock. The transistor-level cells were checked one by one, and the whole converter was checked with Verilog-A behavioural models. A conversion takes 12 clock cycles, giving 12 µs, 83.3 kS/s and a 4.883 mV LSB. With a 10 kHz, 2.5 V ± 0.1 V sine input, bits D9 to D0 come out in order, the output register loads only on the register clock, and the output lags the input by one conversion. The recorded output matches an ideal quantiser in all 40 conversions. INL lies between −0.33 and +0.50 LSB, DNL between −0.42 and +0.39 LSB, there are no missing codes, the SNR is 33.7 dB and the ENOB is 9.95 bits. The kT/C noise of the 10.23 pF array is 20.1 µV rms (0.4% of an LSB).